Pixel circuit with shared active regions

ABSTRACT

An LCD pixel device is provided of the type deployed in a matrix of pixels selectively energized by a plurality of row lines and plurality of column lines and wherein a video voltage is stored on at least one pixel capacitor and coupled to an image-generating device. First and second source regions are formed near the surface of a semiconductor substrate. A drain region is likewise formed in the substrate between the first and second source regions forming the channels of first and second field-effect-transistors. An insulating layer is formed on the substrate, and first and second gate electrodes are provided in the insulating layer between the first source region and the drain region and the second source region and the drain region respectively. First and second mirrors are provided on the surface of the insulating layer. Conductive interconnects formed in the insulating layer provide electrical coupling between the first and second transistors, the first and second capacitors, and the first and second mirrors, respectively.

TECHNICAL FIELD

[0001] This invention relates generally to a liquid crystal display(LCD), and more particularly to an LCD display utilizing miniaturizedpixel cells having shared active regions.

BACKGROUND OF THE INVENTION

[0002] For many decades, the cathode ray tube (CRT) was the dominantdisplay device creating an image by scanning a beam of electrons acrossa phosphor-coated screen causing the phosphors to emit visible light.The beam is generated by an electron gun and is passed through adeflection system that causes the beam to rapidly scan left-to-right andtop-to-bottom. A magnetic lens focuses the beam to create a small movingdot on the phosphor screen. This rapidly moving spot of light paints animage on the surface of the viewing screen.

[0003] Light emitting diodes (LEDs) have also found a multitude of usesin the field of optoelectronics. An LED is a solid-state device capableof converting a flow of electrons into light. By combining two types ofsemiconductive material, LEDs emit light when electricity is passedthrough them. Displays comprised of LEDs may be used to display a numberof digits each having seven segments. Each segment consists of a groupof LEDs, which in combination can form alphanumeric images. They arecommonly used in, for example, digital watch displays, pager displays,cellular handset displays, etc., and due to their excellent brightness,LEDs are often used in outdoor signs. Generally speaking, however, theyhave been used primarily in connection with non-graphic,low-information-content alphanumeric displays. In addition, in alow-power CMOS digital system, the dissipation of LEDs or othercomparable display technology can dominate the total system's powerrequirements, which could substantially negate the low-power dissipationadvantage of CMOS technology.

[0004] Liquid crystal displays (LCDs) were developed in the 1970s inresponse to the inherent limitations in the then existing displaytechnologies (e.g. CRTs, LED displays, etc.) such as excessive size,limited useful life, excessive power consumption, and limitedinformation content. LCD displays comprise a matrix of pixels that arearranged in rows and columns that can be selectively energized to formletters or pictures in black and white or in a wide range of colorcombinations. An LCD modifies light that passes through it or isreflected from it as opposed to emitting light, as does an LED. An LCDgenerally comprises a layer of liquid crystalline material suspendedbetween two glass plates or between a glass plate and a substrate. Aprinciple advantage of an LCD over other display technologies is theability to include thousands or even millions of pixels in a singledisplay paving the way for much greater information content.

[0005] With the shift from segmented, very low information contentdisplays to more information-rich digital products, LCDs now appear inproducts throughout the communications, office automation, andindustrial, medical, and commercial electronics industries.Historically, the market for small displays has demanded low cost,minimal power consumption, and high image quality. It is well known thatimage quality is improved as display resolution increases, and that thiscan be accomplished by increasing the size of the array for a fixedpixel cell size. Unfortunately, system costs increase dramatically asthe diagonal length of the array increases. It is also known that thestored video voltage on each pixel cell capacitor is subject to noisesignals due to capacitive coupling between adjacent rows and columns.Capacitively coupled noise signals on the pixel will result in an imagewhich does not correctly match the stored video signal, and thereforeimage quality is degraded. Increasing the physical separation betweenthe pixel cell capacitor metal interconnect and the row and column linereduces capacitive coupling but has the undesirable effect of requiringa larger pixel cell die area to maintain a fixed capacitance.

[0006] In view of the foregoing, it should be appreciated that it wouldbe desirable to increase the display resolution of an LCD displaywithout increasing display size. Furthermore, it would likewise bedesirable to minimize unwanted capacitive coupling between each pixelcell capacitor and adjacent rows and columns. Additional desirablefeatures will become apparent to one skilled in the art from theforegoing background of the invention and the following detaileddescription of a preferred exemplary embodiment and appended claims.

SUMMARY OF THE INVENTION

[0007] In accordance with the teachings of the present invention, thereis provided an LCD pixel device of the type deployed in a matrix ofpixels that are selectively energized by a plurality of row lines andplurality of column lines and wherein a video voltage is stored on atleast one pixel capacitor and coupled to an image-generating device.First and second source regions are formed near the surface of asemiconductor substrate. A drain region is likewise formed in thesubstrate between the first and second source regions forming thechannels of first and second field-effect-transistors. An insulatinglayer is formed on the substrate, and first and second gate electrodesare provided in the insulating layer between the first source region andthe drain region and between the second source region and the drainregion, respectively. First and second mirrors are provided on thesurface of the insulating layer. Conductive interconnects formed in theinsulating layer provide electrical coupling between the first andsecond transistors, the first and second capacitors, and the first andsecond mirrors, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention will hereinafter be described inconjunction with the accompanying drawings wherein like referencenumerals denote like elements, in which:

[0009]FIG. 1 is a schematic diagram of a single analog pixel cell;

[0010]FIG. 2 is a simplified functional diagram illustrating how pixelcircuitry interacts with pixel mirrors and the remainder of an LCDmicrodisplay;

[0011]FIG. 3 is a simple cross-sectional view showing major componentsof an LCD microdisplay;

[0012]FIG. 4 is a partial schematic/partial block diagram of an N×M LCDdisplay utilizing video switches in accordance with the presentinvention;

[0013]FIG. 5 is a schematic diagram of two adjacent pixel cells inaccordance with the teachings of the present invention; and

[0014]FIG. 6 is a cross-sectional view of a portion of an LCD displayillustrating the use of adjacent NMOS access transistors having a shareddrain and pixel video guard rings in accordance with the teachings ofthe present invention.

DESCRIPTION OF THE PREFERRED EXEMPLARY EMBODIMENT

[0015] The following detailed description of a preferred embodiment ismainly exemplary in nature and is not intended to limit the invention orthe application or use of the invention.

[0016]FIG. 1 is a schematic diagram of an individual pixel 20 coupled toa row line 22 and a column line 24. Of course it should be understood,that an actual LCD microdisplay would include a large matrix of rowlines 22, column lines 24, and pixels 20. Each pixel includes an accessn-channel field-effect-transistor 26, which has a gate coupled to rowline 22 and a drain coupled to column line 24. The source of accesstransistor 26 is coupled to a first terminal of pixel capacitor 28 andto pixel mirror 30, the function of which will be described more fullyin connection with FIG. 2. The other terminal of capacitor 28 is coupledto a source of potential; e.g. ground.

[0017]FIG. 2 is a simplified functional diagram illustrating how eachpixel 20 interacts with an associated mirror 30 to create a liquidcrystal image. FIG. 3 is a simplified cross-sectional view of a liquidcrystal display that likewise will be useful in explaining the operationof a liquid crystal display. In both cases, like reference numeralsdenote like elements. Referring to both FIG. 1 and FIG. 2, pixel 20,described in connection with FIG. 1, is again shown coupled to mirror30, a plurality of which reside on the surface of a semiconductorsubstrate (e.g. silicon) 32 as is shown in FIG. 3. Mirrors 30 may bemetallic (e.g. aluminum) and have a thickness of, for example, 2000angstroms, and each has a reflective surface 34 that may or may not haveenhanced reflective properties. When row line 22 is asserted, transistor26 becomes conductive, thus permitting the video signal (e.g. a analogvideo signal) appearing on column line 24 to charge pixel capacitor 28.Thus, the voltage on mirror 34 will vary in accordance with the voltageacross pixel capacitor 28. Located within region 38 is a liquid crystalmaterial, the molecules of which orient themselves in a relationshipthat depends on the voltage applied thereacross. A glass seal 46 isprovided under which a layer of indium-tin-oxide (ITO) 40 is providedwhich is a transparent conductive material to which a potential V_(com)is applied as is shown at 42. V_(com) may, for example, be approximately7 volts. The voltage stored across pixel capacitor 28 and therefore thevoltage on mirror 34 may approach a much higher voltage (e.g. 17-18volts) thus placing a significant potential difference between mirror 34and ITO layer 40 and causing the molecules of the liquid crystalmaterial in region 38 to assume a first orientation corresponding toblack. Alternatively, if the voltage stored across pixel capacitor 28 islow, thus reducing the potential difference between mirror 30 and ITOlayer 40, the molecules of the liquid crystal material in region 38 willassume a different orientation (e.g. corresponding to white). That is, ahigh voltage on mirror 30 may cause the molecules of the liquid crystalmaterial to substantially prevent light (indicated by arrow) 44 frombeing reflected from mirror surface 34 while a lower voltage on mirror30 will permit light 44 to be reflected.

[0018] Mirrors 30 reside on the surface of a semiconductor substrate(e.g. silicon) 32, which has deposited therein or formed thereon all theactive regions (e.g. pixel capacitors, access transistors, etc.)required to produce a working device. Semiconductor die is supported bya substrate 50 (e.g. ceramic) which may have a flexible printed circuitboard 52 disposed thereon for the purpose of making external connectionto semiconductor die 32 and ITO layer 40 by, for example, wire bond 54and conductive epoxy crossover 56. Finally, a perimeter seal 58 isprovided between the surface of semiconductor dye 32 and the surface ofITO layer 40 to seal the liquid crystal material within region 38.

[0019] In operation, ambient or generated light (indicated by arrows 60)impinges upon and passes through transparent glass layer 46 and ITOlayer 40. If the potential difference between mirror 30 and ITO layer 42is high, virtually no light will be reflected from surface 34 of mirror30 and therefore that portion of the video image created by pixel 20will approach black. If, on the other hand, the potential differencebetween mirror 30 and ITO layer 42 is very low, virtually all of thelight 60 striking surface 34 will be reflected and that portion of thevideo image to be created by pixel 20 will approach white. It should beclear that between these two extremes, there are a multiple of shadesextending from white to black, which may be displayed depending on themagnitude video voltage stored on pixel capacitor 28 and applied tomirror 30. Since the operation and structure of liquid crystalmicrodisplays is well known and well documented in technical literature.For example, see U.S. Pat. No. 3,862,360 entitled “Liquid CrystalDisplay System With Integrated Signal Display Storage Circuitry” issuedJan. 21, 1975 and assigned to Hughes Aircraft Company, the teachings ofwhich are hereby incorporated by reference.

[0020]FIG. 4 is a partial schematic/partial block diagram of an N×M LCDmicrodisplay utilizing video switches in accordance with the teachingsof the present invention. As can be seen, the apparatus of FIG. 4comprises an N×M matrix 60 of video pixels 20 (only several of which areshown for clarity), a plurality of rows R1, R2, . . . , RN, and aplurality of columns C1, C2, . . . , CM. The apparatus also includes afirst row select circuit 62, a first column select circuit 64 andoptionally a second row select circuit 66. Row select circuit 62includes a shift register containing bits SR21, SR22, . . . , SR2N, theoutput of each of which is respectively coupled to a plurality of rowdrivers RD11, RD12, . . . RD1N. Similarly, column select circuit 64includes a serial shift register comprised of bits SR11, SR12, . . . ,SR1M each having outputs coupled respectively to video switches VX1,VX2, . . . , VXN.

[0021] As is well known in the art, the pixels coupled to the columnsand rows are scanned in order to create an LCD image. The following isone example of how this scanning process is accomplished. Starting withrow select circuitry 62, shift register bit SR21 has a signal 68 appliedto an input thereof. Under the control of a row clock applied to theclock input 70 of bit SR21 and to the clock inputs of each successivestage SR22, . . . , SR2N, signal 68 is propagated through the shiftregister. The output of each shift register bit is coupled to acorresponding row driver RD11, RD12, . . . , RD1N each of which issequentially energized as signal 68 propagates through the bits of theshift register. This process in turn sequentially asserts rows R1, R2, .. . , RN.

[0022] Column select circuit 64 likewise comprises a shift registercomprised of shift register bits SR11, SR12, . . . , SR1M each of whichhas an output coupled respectively to a plurality of column videoswitches VX1, VX2, . . . , VXM. The output of each video switch VX1,VX2, . . . , VXM is coupled respectively to columns C1, C2, . . . , CM.Each video switch also has an input for receiving the video signal to bedisplayed as is shown at 72. A pulse signal 74 is applied to the inputof the first shift register bit SR11, and through the action of a columnclock which is applied to the clock inputs of each of the shift registerbits SR11, SR12, . . . , SR1M, pulse 74 is serially clocked throughsuccessive bits of the shift register. Thus, each of the video switchesVX1, VX2, . . . , VXM each has an input which is respectively coupled toa corresponding output of a shift register bit for sequentially applyingthe video signal appearing at 72 to each of the column lines C1, C2, . .. , CM.

[0023] If desired, a second row select circuit 66 may be provided todrive the row lines at their opposite ends in order to provide a greaterdrive capacity. Circuit 66 includes a shift register comprised of stagesSR31, SR31, . . . , SR3M and a plurality of row drivers RD21, RD22, . .. , RD2N. SR31 receives the same input signal 68 and row clock at 72 soas to operate synchronously with row select circuit 62. Thus, instead ofdriving the matrix rows from only one end and propagating the drivesignal down the entire row, each row is driven at both ends to improveperformance.

[0024] As stated previously, it would be desirable to increase displayresolution without increasing display size and to limit unwantedcapacitive coupling between the pixel cell capacitor and adjacent rowsand columns without sacrificing die area. FIG. 5 is a schematic diagramof two adjacent pixel cells in accordance with the teachings of thepresent invention. The first pixel cell comprises access n-channelfield-effect-transistor 90, capacitor 94 and mirror 80.Field-effect-transistor 90 has a gate coupled to row line 86 and asource coupled to a first terminal or capacitor 94 which has a secondterminal for coupling to a potential (e.g. ground). As can be seen,capacitor 94 is coupled to a first mirror 80. Similarly, n-channelfield-effect-transistor 92 has a gate coupled to row line 88 and asource coupled to a first terminal of capacitor 96 which has a secondterminal for coupling to a potential (e.g. ground). Capacitor 96 iscoupled to mirror 82. It should be noted that the drains of bothtransistors 90 and 92 are coupled in common and to column line 84. It isthis feature that helps achieve the desired miniaturization which inturn enables an increase in display resolution without an increase indisplay size, as will be more fully explained in connection with FIG. 6.

[0025]FIG. 6 is a cross-sectional view of a portion of an LCD displaywherein adjacent access transistors share a common drain region.Referring to FIG. 6, there is shown a semiconductor substrate (e.g.p-doped silicon) into which n-doped regions 98, 100 and 102 are formed.Region 98 corresponds to the source of transistor 90, region 102corresponds to the source of transistor 92, and region 100 correspondsto the common drain of transistors 90 and 92 as shown in FIG. 5. A gateelectrode 104 is formed on the surface of substrate 32 in the regionbetween source region 98 and drain region 100 forming a channeltherebetween. Similarly, gate electrode 106 is formed on the surface ofsubstrate 32 between source region 102 and drain region 100 forming achannel therebetween. Gate 104 is coupled to a first row line 86 (FIG.5) via metal interconnect 108, and gate 106 is coupled to a second rowline 88 via metal interconnect 110. Gates 104 and 106 and interconnects108 and 110 are formed in an insulating layer deposited on substrate 32made of, for example, a silicon oxide (e.g. silicon dioxide).

[0026] Source region 98 is likewise electrically coupled to a firstplate 110 and top electrode of a polysilicon capacitor via metalinterconnect 112. The second plate 114 and bottom electrode of thepolysilicon capacitor is formed on the surface of field oxide 116 (e.g.silicon dioxide). In like fashion, source region 102 is coupled to afirst plate 118 of a second polysilicon capacitor via metal interconnect120. The second plate 122 resides on a region 124 of field oxide (e.g.silicon dioxide). Capacitor plate 110 is coupled to mirror 80 formed oninsulating layer 131 via metal interconnect 112 and metal connect 126.In a similar fashion, capacitive plate 118 is electrically coupled tomirror 82 formed on insulating layer 131 via metal interconnect 120 andmetal interconnect 128. Mirrors 80 and 82 reside in a region 38 occupiedby a liquid crystal material as shown and described in connection withFIG. 2 and FIG. 3. Glass lens 46 is formed on ITO layer 40 to form theupper boundary of the liquid crystal material as was also described inconnection with FIG. 2 and FIG. 3.

[0027] Thus, a first access transistor (90 in FIG. 5) is formed bysource region 98, drain region 100, and gate 104, and a second accesstransistor (92 in FIG. 5) is formed by source 102, drain 100 and gate106. The source of the first transistor (P-type region 98) is coupled toa video storage capacitor (94 in FIG. 5) formed by plates 110 and 114,which are in turn coupled to pixel mirror 80. In a similar fashion, thesecond access. transistor (92 in FIG. 5) is coupled to a video storagecapacitor (96 in FIG. 5) formed by plates 118 and 122, which are in turncoupled to mirror 82. Through the use of a common drain region, die areais saved and the number of pixels may be increased, thereby increasingdisplay resolution without increasing display size.

[0028] To limit the capacitive coupling between the pixel cellcapacitors and the adjacent rows and columns, a guard ring electricallyconnected to the ground potential 130 encircles metal interconnect 120thereby electrically isolating it from adjacent column line 132 andadjacent row line 134. Similarly, a guard ring 136 encirclesinterconnect 112 to isolate it from column line 132 and row line 138.This helps reduce the occurrence of noise signals on pixel cellcapacitors due to the capacitive coupling between the pixel capacitorsand adjacent rows and column signal lines.

[0029] From the foregoing description, it should be appreciated that anarrangement has been provided wherein two adjacent pixel cells share acommon drain region. This results in a reduction in the amount of diearea that would be required if each pixel access transistor had aseparate drain region. Furthermore, since the metal interconnectscontacting the video storage capacitors are protected by grounded guardrings, the amount of noise on the pixel cell capacitors due tocapacitive coupling between the capacitors and adjacent rows and columnsis reduced.

[0030] While a preferred exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations in the embodiments exist. It should also beappreciated that this preferred embodiment is only an example and is notintended to limit the scope, applicability or configuration of theinvention in any way. Rather, the foregoing detailed descriptionprovides those skilled in the art with a convenient roadmap forimplementing the preferred exemplary embodiment of the invention.Various changes may be made in the function and arrangement describedabove without departing from the spirit and scope of the invention asset forth in the appended claims.

1-25. (canceled)
 26. A method, in a liquid crystal display (LCD), forproviding a matrix of pixels selectively energized by a plurality of rowlines and a plurality of column lines and wherein a video voltage isstored on at least one pixel capacitor coupled to an image-generatingdevice, said method comprising the steps of: providing a substratehaving a first surface; forming first and second source regions on thesubstrate proximate to the first surface; forming a drain region on thesubstrate proximate to the first surface and between the first andsecond source regions; forming a first channel of a firstfield-effect-transistor between the first source region and the drainregion; forming a second channel of a second field-effect-transistorbetween the second source region and the drain region; forming aninsulating layer having a second surface on the first surface; formingfirst and second gate electrodes in the insulating layer proximate thefirst channel and the second channel, respectively, and coupled to firstand second ones, respectively, of a plurality of row lines; forming adrain electrode in the insulating layer; coupling the drain electrode toone of a plurality of column lines; forming first and second capacitorsin the insulating layer; forming first and second mirrors on the secondsurface; and forming first and second interconnects in the insulatinglayer for providing electrical coupling between the first source region,the first capacitor, and the first mirror, and between the second sourceregion, the second capacitor, and the second mirror, respectively. 27.The method according to claim 26, wherein the substrate is a p-dopedsilicon substrate.
 28. The method according to claim 27, wherein thefirst and second source regions are n-doped silicon.
 29. The methodaccording to claim 28 wherein the drain region is n-doped silicon. 30.The method according to claim 29, wherein the insulating layer issilicon dioxide.
 31. The method according to claim 30, wherein the firstand second capacitors are polysilicon capacitors.
 32. The methodaccording to claim 31 wherein the first and second mirrors are aluminum.33. The method according to claim 32 wherein the first and secondinterconnects are aluminum.
 34. The method according to claim 26,further comprising the step of deploying first and second guard ringsaround the first and second interconnects, respectively.
 35. A method,in a liquid crystal display (LCD), for generating an image from a videosignal, the LCD having a matrix of pixels arranged in a plurality ofrows and a plurality of columns which are selectively energized tocreate the image of the video signal, said method comprising the stepsof: providing at least first and second row lines; providing at leastone column line; providing a substrate having a first surface; formingfirst and second source regions in the substrate proximate to the firstsurface; forming a drain region in the substrate proximate to the firstsurface and between the first and second source regions; forming a firstchannel of a first field-effect-transistor between the first sourceregion and the drain region; forming a second channel of a secondfield-effect-transistor between the second source region and drainregion; forming an insulating layer on the first surface; forming firstand second gate electrodes in said insulating layer proximate to thefirst channel and said second channel, respectively, and coupled to theat least first and second row lines, respectively; forming a drainelectrode in the insulating layer; coupling the drain electrode to theat least one column line; forming first and second capacitors in theinsulating layer; forming first and second mirrors on the secondsurface; and forming first and second interconnects in the insulatinglayer for providing electrical coupling between the first source region,the first capacitor, the said first mirror, and between the secondsource region, the second capacitor, and the second mirror,respectively.
 36. The method according to claim 35, wherein thesubstrate is a p-doped silicon.
 37. The method according to claim 36,wherein the first and second source regions and the drain regions are an-doped silicon.
 38. The method according to claim 37, wherein the firstand second capacitors are polysilicon capacitors.
 39. The methodaccording to claim 38, wherein the first and second mirrors arealuminum.
 40. The method according to claim 35 further comprising thestep of deploying first and second guard rings around the first andsecond interconnects, respectively.